Emre Ceylan
Why quartz crystals fail to oscillate is one of the most common sentences we hear on the prototype bench. The board does not boot, UART stays silent, the RTOS never starts — and the team looks at firmware first, then the MCU. Yet lab measurements show the problem is often hidden not in the crystal circuit itself but in the PCB layout.
This article covers four elusive mistakes we see again and again at Revan Technology. A board that “sometimes works” on the bench goes completely silent in mass production or at cold temperature. Checking these items during PCB design cuts field debug time from weeks to hours.
Quartz crystal and PCB layout — brief definition
The internal MCU oscillator circuit drives an external quartz crystal to oscillate at a defined frequency. The crystal connects to XTAL1/XTAL2 (or OSC_IN/OSC_OUT) pins; load capacitors (CL) sit between each pin and ground. Total load capacitance must match the value in the crystal datasheet.
On the PCB, trace length, layer transitions, ground-plane continuity and neighbouring noise sources invisibly degrade this network. Why quartz crystals fail to oscillate is often not a single wrong capacitor but a parasitic L-C network and a weak ground return.
Problem context
The customer holds a board where the crystal “looks correct, right frequency.” The same circuit works on a breadboard; 12 of the first 50 boards from the fab never boot. On the scope, XTAL pins show a flat line or millivolt-level noise. The developer disables the watchdog — still no result.
This pattern appears often on industrial boards with external 8–25 MHz crystals on STM32, ESP32 or PIC. The issue is blamed on a “bad crystal”; stock is swapped, CL values are tweaked at random. The real root cause usually sits in four points that look correct on the schematic but break in layout.
Technical analysis — 4 elusive PCB mistakes
1. Wrong or copy-paste load capacitors
Datasheet formula: CL = (C1×C2)/(C1+C2) + Cstray. Cstray includes pad, via and trace capacitance. 22 pF is copied from a reference design; on a four-layer board with different pad sizes the real load drifts to 18 pF — the crystal is out of spec, oscillation does not start or frequency drifts.
2. Crystal far from MCU pins — long traces and unnecessary vias
The crystal should sit millimetres from the MCU; traces short, symmetric and on the same layer. A 15–20 mm trace plus two vias raises parasitic capacitance and eats Pierce oscillator margin. “Never oscillates” at cold or low supply often starts here.
3. Broken ground plane under the crystal or weak GND return
Crystal and CL capacitors need a continuous ground plane below; digital traces must not run underneath. A wide slot or split ground breaks the oscillator loop reference. Noise enters the crystal net capacitively or via high impedance; oscillation never starts or jitter rises.
4. Proximity to relays, motor drivers or fast digital lines
Relay drive, SPI or switch-mode power routed next to the crystal net “silences” the oscillator from outside. On industrial boards, a relay coil neighbour looks like instant crystal lock-up — in reality EMI exhausts oscillation margin. Guard ring and physical separation are mandatory.
Field scenarios
- Cold-storage IoT gateway: No boot at -20 °C; CL values chosen for 25 °C, stray capacitance ignored.
- Relay-board PLC module: MCU resets when the relay pulls; crystal traces pass 3 mm from the relay driver.
- Four-layer prototype → two-layer production: Vias reduced but crystal left far away; 15% boot failure in series build.
- External 32 kHz RTC crystal: Watchdog and RTC used together; long RTC trace, oscillator never starts in backup-battery mode.
Solution approaches
First measure XTAL pins on a scope — if there is no oscillation, do not move to firmware. Recalculate CL values with your PCB’s stray capacitance; trim if needed (fixed value locked for production). Place the crystal as close as possible to the MCU, symmetrically; keep vias to a minimum.
Provide an uninterrupted ground plane under the crystal; keep digital and power traces away with a guard ring. Physically separate relay/motor zones from the oscillator zone; shield the crystal if needed. These items go on the checklist in PCB design revision and are rechecked at DFM.
Benefits
Correct oscillator placement dramatically cuts boot-failure rate; fewer “dead board” swaps in the field. Frequency stability and UART/USB reliability improve. “Sometimes works” behaviour disappears in cold/heat tests. Lab debug time shrinks; production scrap drops.
Industry observation / experience
In Revan projects the crystal circuit is not a detail “fixed later.” Even with a correct schematic, a layout error is one of the most expensive debug types in industrial field work — because the fault does not show up in software logs. A hand-soldered crystal works on the prototype; after SMT reflow the same values leave the board silent. That gap usually hides in one of the four points above.
Conclusion
Why quartz crystals fail to oscillate is usually not the MCU or firmware but PCB layout mistakes involving load capacitors, trace length, ground plane and neighbouring noise. Checking these four points early in the lab is the cheapest insurance before mass production.
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